The present invention relates to a thin film transistor (hereinafter referred to as a TFT) having a non-single crystalline silicon film and provided on an insulating film formed on an insulating substrate like glass or other various types of substrates, or a thin film integrated circuit as an application thereof, in particular, for an active type liquid crystal display (LCD), and a manufacturing method thereof.
The Si TFTs can be classified into amorphous silicon TFTs and polysilicon (or polycrystalline silicon) TFTs depending on the type and crystallization conditions of the semiconductor material thereof.
Meanwhile, there has also been made research into those semiconductor materials which have crystallization conditions intermediate between amorphous silicon and polysilicon. Although there is an argument as to the intermediate crystallization conditions, any silicon which is crystallized more or less by any method such as thermal annealing at temperatures exceeding 450.degree. C. or irradiation with laser beams, high intensity light beams, and other high energies will be referred to as polysilicon in the present specification.
Further, polysilicon TFTs are also applied as to so called SOI (semiconductor on insulation) technique for monocrystalline silicon integrated circuits and used as load transistors, for example, in highly integrated static random access memories (SRAMs). It should be noted here that amorphous TFT is hardly used for this purpose.
Since a semiconductor circuit having a TFT on an insulating substrate has no capacity coupling between the substrate and wiring thereof, it allows high operational speeds, thus realizing ultra fast microprocessors and memories.
Generally, amorphous semiconductor has a small electric field mobility and cannot therefore be used for TFTs required of high operational speeds. Also, P-type amorphous silicon has too small an electric field mobility to produce P-channel TFTs (PMOS TFTs) and therefore form complementary MOS (CMOS) circuits in combination with N-channel TFTs (NMOS TFTs).
However, TFTs formed of an amorphous semiconductor can have a smaller Ioff current. Accordingly, an amorphous channel TFT can be applied to those devices in which a high operation speed is not so required for TFTs, and TFTs of only one conductivity type are enough and a large charge retention capability is required, for example, an active matrix circuit for an LCD device of a small matrix size.
On the other hand, a polycrystalline semiconductor has a larger electric field mobility and therefore allows higher operational speeds than an amorphous semiconductor. For example, a TFT using a silicon film recrystallized through laser annealing has an electric field mobility as high as 300 cm.sup.2 /Vs. This value is extremely large considering that a MOS transistor formed on an ordinary monocrystal silicon substrate has an electric field mobility in the order of 500 cm.sup.2 /Vs. While a MOS circuit formed on a monocrystalline silicon substrate allows only limited operational speeds due to parasitic capacity present between substrate and wiring thereof, a TFT mounted on an insulating substrate is free from those limitations and expected to allow considerably high operational speeds.
Further, polysilicon can be used not only for NMOS TFTs but also for PMOS TFTs and can therefore form CMOS circuits, thus realizing a so called monolithic structure as in active matrix type liquid crystal displays wherein polycrystalline CMOS TFTs constitute not only the active matrix portion but also peripheral circuits thereof (drivers, etc.). A pMOS TFT as a load transistor is constituted by polysilicon also in the SRAM mentioned before.
In amorphous TFTs, it is difficult to form the source and drain regions through a self-aligning process which is used for a monocrystalline IC technology so that parasitic capacity resulting from the geometrical overlapping of the gate electrode with the source and drain electrodes undesirably occurs. On the contrary, polysilicon TFTs are more advantageous in that the self-aligning process can be employed, thus suppressing the parasitic capacity.
However, polysilicon TFTs suffer from larger more leakage current (also called off-state current) in the absence of voltage to the gate electrode thereof (in the off-state thereof) than amorphous TFTs. Consequently, when polysilicon TFTs are used at pixel electrodes of liquid crystal displays, measures have been implemented to provide auxiliary capacity to compensate for the leakage current and further connect two polysilicon TFTs in series to reduce leakage current.
Also, it is known to take advantage of the high off-state resistance of amorphous silicon TFTs and further form the peripheral circuits with polysilicon TFTs having a high electric field mobility on the same substrate. This can be realized by forming amorphous silicon and irradiating it selectively with laser beams to crystallize only the peripheral circuits.
At present, however, the production yield of the above method is low due to low reliability of the laser irradiation process (e.g. poor uniformity of irradiated energy per unit area). Also, since amorphous silicon TFTs with a low electric field mobility are used in the active matrix region, it is difficult to use this method for higher level applications. Instead of the laser irradiation process, a thermal annealing of a higher reliability and lower cost is desired. Also, it is desired that TFTs have an electric field mobility of at least 5 cm.sup.2 /Vs to enhance added product values.
In conventional liquid crystal displays, it is known that TFTs constituting decoder/driver circuit and TFTs provided at pixel electrodes arranged in a matrix form are formed on the same substrate. It is not, however, that liquid crystal displays operate only with the decoder and driver circuits and pixel electrodes; they also require CPU and memory circuits, which have conventionally been provided externally and connected with the decoder and driver circuits formed on the glass substrate through such means as wire bonding. This configuration causes the problems of increased manufacturing processes and reduced reliability.
Meanwhile, these amorphous or polycrystalline silicon (collectively referred to as non single crystalline silicon) causes much greater grain boundary effects than monocrystalline silicon used in monocrystalline semiconductor integrated circuits. The typical example is a leakage current between source and drain regions. In particular, leakage current (also-called off current) when applying a reverse bias voltage (negative for N-channel transistors and positive for P-channel transistors) to a gate electrode is caused by the existence of grain boundaries and known to deteriorate the operating characteristics of transistors.
The off-state current is caused by abrupt variations in the electric field at the boundary between the impurity region (N-type or P-type region) of source and drain regions and the channel forming region (substantially intrinsic). While this does not cause a problem in monocrystalline silicon, in the case of a non single crystalline silicon, carriers hop from the conduction band (valence electron band) of the impurity diffused region to the conduction band (valence electron band) of the channel forming region through grain boundaries.
As in monocrystalline MOS devices, an attempt has been made to solve this problem by providing an offset region for relieving the electric field or a low doped drain (LDD) structure for lowering the impurity density of the impurity diffused region.
Referring to FIG. 2 (A), there is shown a conceptual diagram illustrating a conventional offset gate type TFT. Its active layer is roughly divided into three regions. The first region is an impurity region with a high impurity concentration (source and drain regions), designated by 13 and 17 in FIG. 2 (A). The second region is called an offset region or an LDD region, designated by reference numerals 14 and 16. The second region has a high resistance while it is substantially intrinsic or has the same conduction type as the source and drain regions in such a degree that the parasitic channel is suppressed. There is no gate electrode overlapping the second region. The third region is a channel forming region, designated by reference numeral 15. This region is capable of varying the conductivity type and controlling the flow of carriers under the influence of the gate electrode 11 through the gate insulating film 12.
FIG. 2B shows an energy band diagram with respect to an active layer in the vicinity of a gate insulating layer in an N channel TFT when there is no voltage applied to a gate electrode and a voltage between source and drain regions is enough small. Here, E.sub.F is a Fermi level, E.sub.1 and E.sub.N is a band gap of the channel forming region and the impurity region, respectively. Normally, E.sub.1 =E.sub.N. Also, a band gap of an offset region is the same as E.sub.1. The band gap diagram when applying a reverse bias voltage (i.e. negative voltage) to the gate electrode with the source/drain voltage unchanged is shown in FIG. 2C. As can been seen, the potential of the channel region adjacent to the gate electrode is changed by "E.sub.G ".
It should be noted that the electric field in a boundary region between the channel forming region and the impurity region is varied moderately because of the existence of the offset regions 14 and 16, resulting in a decrease in a leak current in this region. However, when the source/drain voltage (forward bias voltage) is increased, the band in the drain region 17 shifts to a lower portion than that shown in FIG. 2C with the continuous line. As a result, the electric field across the channel forming region 15 and the drain region 17 becomes steep, causing a leak current through grain boundaries.
The above analysis can be proved by experiments where a leak current is not so remarkable when the voltage V.sub.D between the source and drain region is small, it increases as the V.sub.D increases, and it becomes more larger when the reverse bias voltage (i.e. a negative voltage in the case of a NTFT) increases. See FIG. 2D.
Accordingly, the electric field in a region between the channel and drain regions has to change moderately even when the source/drain voltage V.sub.D is large in order to reduce the leak current.
In particular, the foregoing problem is more significant when the active layer contains a metallic element for promoting a crystallization thereof even though the concentration of the element is very small. Examples of the metallic element are Ni, Fe, Co, Ru, Rh, Pd, Os, Ir, Pt, Sc, Ti, V, Cr, Mn, Cu, Zn, Au, and Ag. These elements are added in a silicon semiconductor in order that a crystallization temperature of the non-crystalline silicon is lowered and the time for crystallization can be reduced. However, these elements tend to form intermediate levels within the band gap and have a same function as grain boundaries, resulting in an increase of a leak current.